Working on PCB layout for v1.2.0

Browse Source

...

This commit is contained in:

David

2012-07-30 03:40:42 +00:00

parent 845d3c2f20

commit 954f14fc3a

3 changed files with 0 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download Patch File Download Diff File Expand all files Collapse all files

BIN

trunk/PowerLock BOM Calculations.xlsm

Binary file not shown.

BIN

trunk/PowerLock EL/Schematic/PowerLock_PIC.brd

Binary file not shown.

BIN

trunk/PowerLock EL/Schematic/PowerLock_PIC.sch

Binary file not shown.