diff --git a/trunk/PowerLock Calculations.xlsx b/trunk/PowerLock Calculations.xlsx
deleted file mode 100644
index 895fbc4..0000000
Binary files a/trunk/PowerLock Calculations.xlsx and /dev/null differ
diff --git a/trunk/PowerLock Data Sheet.docx b/trunk/PowerLock Data Sheet.docx
index d4d7fcb..a71702b 100644
Binary files a/trunk/PowerLock Data Sheet.docx and b/trunk/PowerLock Data Sheet.docx differ
diff --git a/trunk/PowerLock EL/Schematic/PowerLock_PIC.brd b/trunk/PowerLock EL/Schematic/PowerLock_PIC.brd
index 08bee4a..3b17047 100644
Binary files a/trunk/PowerLock EL/Schematic/PowerLock_PIC.brd and b/trunk/PowerLock EL/Schematic/PowerLock_PIC.brd differ
diff --git a/trunk/PowerLock EL/Schematic/PowerLock_PIC.sch b/trunk/PowerLock EL/Schematic/PowerLock_PIC.sch
index f0e1693..167bbe7 100644
Binary files a/trunk/PowerLock EL/Schematic/PowerLock_PIC.sch and b/trunk/PowerLock EL/Schematic/PowerLock_PIC.sch differ
diff --git a/trunk/PowerLock EL/Simulations/Load Dump - 24v system.asc b/trunk/PowerLock EL/Simulations/Load Dump - 24v system.asc
index 8b0737e..58fd1a1 100644
--- a/trunk/PowerLock EL/Simulations/Load Dump - 24v system.asc	
+++ b/trunk/PowerLock EL/Simulations/Load Dump - 24v system.asc	
@@ -1,5 +1,12 @@
 Version 4
 SHEET 1 1152 948
+WIRE 160 -736 112 -736
+WIRE 272 -736 224 -736
+WIRE 336 -736 272 -736
+WIRE 496 -736 336 -736
+WIRE 272 -704 272 -736
+WIRE 336 -704 336 -736
+WIRE 112 -464 112 -736
 WIRE 480 -464 112 -464
 WIRE 576 -464 560 -464
 WIRE 656 -464 576 -464
@@ -14,9 +21,8 @@ WIRE -432 -96 -448 -96
 WIRE -288 -96 -352 -96
 WIRE -160 -96 -288 -96
 WIRE 0 -96 -160 -96
-WIRE 80 -96 0 -96
 WIRE 112 -96 112 -464
-WIRE 112 -96 80 -96
+WIRE 112 -96 0 -96
 WIRE 240 -96 112 -96
 WIRE 320 -96 240 -96
 WIRE 464 -96 400 -96
@@ -36,7 +42,8 @@ WIRE -448 96 -448 32
 WIRE -288 96 -288 32
 WIRE -160 96 -160 32
 WIRE 512 96 240 96
-WIRE 80 432 80 -96
+WIRE 512 128 512 96
+WIRE 528 128 512 128
 WIRE 160 432 80 432
 WIRE 240 432 160 432
 WIRE 432 432 240 432
@@ -98,6 +105,10 @@ FLAG 160 720 0
 FLAG 240 624 0
 FLAG 1040 624 OUT
 FLAG 160 544 0
+FLAG 272 -640 0
+FLAG 336 -640 0
+FLAG 496 -736 Vin_3v3
+IOPIN 496 -736 BiDir
 SYMBOL voltage -448 80 R0
 WINDOW 3 -99 161 Left 2
 WINDOW 123 0 0 Left 2
@@ -111,13 +122,10 @@ SYMATTR InstName D1
 SYMATTR Value DFLZ33
 SYMBOL res 224 0 R0
 SYMATTR InstName R1
-SYMATTR Value 25K
+SYMATTR Value 2K
 SYMBOL res 224 80 R0
 SYMATTR InstName R2
-SYMATTR Value 2K
-SYMBOL npn 512 48 R0
-SYMATTR InstName Q1
-SYMATTR Value 2N3904
+SYMATTR Value 25K
 SYMBOL npn 528 -32 R270
 SYMATTR InstName Q2
 SYMATTR Value 2N3904
@@ -239,6 +247,26 @@ SYMATTR SpiceLine pwr=14w
 SYMBOL cap 144 448 R0
 SYMATTR InstName C6
 SYMATTR Value 2.2µ
+SYMBOL diode 160 -720 R270
+WINDOW 0 32 32 VTop 2
+WINDOW 3 0 32 VBottom 2
+SYMATTR InstName D7
+SYMBOL polcap 256 -704 R0
+WINDOW 3 24 56 Left 2
+SYMATTR Value 22µ
+SYMATTR InstName C7
+SYMATTR Description Capacitor
+SYMATTR Type cap
+SYMATTR SpiceLine V=63 Irms=170m Rser=1 Lser=0 mfg="Nichicon" pn="UPG1J220MPH" type="Al electrolytic"
+SYMBOL polcap 320 -704 R0
+WINDOW 3 24 56 Left 2
+SYMATTR Value 0.47µ
+SYMATTR InstName C8
+SYMATTR Description Capacitor
+SYMATTR Type cap
+SYMATTR SpiceLine V=50 Irms=22m Rser=3.9 Lser=0 mfg="Nichicon" pn="UPL1HR47MAH" type="Al electrolytic"
+SYMBOL nmos 528 48 R0
+SYMATTR InstName M1
 TEXT -480 280 Left 2 !.tran 3s
 TEXT -504 -152 Left 2 ;This simulates a Load Dump on a 24v System
 TEXT 544 -552 Left 2 ;Analog Input intrinsic diode and\nsmall R for current measurement
diff --git a/trunk/PowerLock System Diagrams.vsd b/trunk/PowerLock System Diagrams.vsd
index 047a422..a67fd7a 100644
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