diff --git a/trunk/PowerLock Calculations.xlsm b/trunk/PowerLock Calculations.xlsm
index 2d6d847..c56e7c6 100644
Binary files a/trunk/PowerLock Calculations.xlsm and b/trunk/PowerLock Calculations.xlsm differ
diff --git a/trunk/PowerLock EL/Schematic/PowerLock_PIC.brd b/trunk/PowerLock EL/Schematic/PowerLock_PIC.brd
index 3b17047..5341738 100644
Binary files a/trunk/PowerLock EL/Schematic/PowerLock_PIC.brd and b/trunk/PowerLock EL/Schematic/PowerLock_PIC.brd differ
diff --git a/trunk/PowerLock EL/Schematic/PowerLock_PIC.sch b/trunk/PowerLock EL/Schematic/PowerLock_PIC.sch
index 167bbe7..dfedcf7 100644
Binary files a/trunk/PowerLock EL/Schematic/PowerLock_PIC.sch and b/trunk/PowerLock EL/Schematic/PowerLock_PIC.sch differ
diff --git a/trunk/PowerLock EL/Simulations/Load Dump - 24v system.asc b/trunk/PowerLock EL/Simulations/Load Dump - 24v system.asc
index 58fd1a1..af27738 100644
--- a/trunk/PowerLock EL/Simulations/Load Dump - 24v system.asc	
+++ b/trunk/PowerLock EL/Simulations/Load Dump - 24v system.asc	
@@ -29,21 +29,21 @@ WIRE 464 -96 400 -96
 WIRE 528 -96 464 -96
 WIRE 848 -96 624 -96
 WIRE 864 -96 848 -96
-WIRE 240 -48 240 -96
 WIRE -448 -32 -448 -96
 WIRE -288 -32 -288 -96
 WIRE -160 -32 -160 -96
 WIRE 576 -16 576 -32
 WIRE 576 -16 464 -16
+WIRE 240 16 240 -96
 WIRE 576 32 576 -16
-WIRE 576 48 576 32
+WIRE 576 80 576 32
 WIRE 864 80 864 -96
 WIRE -448 96 -448 32
 WIRE -288 96 -288 32
 WIRE -160 96 -160 32
-WIRE 512 96 240 96
-WIRE 512 128 512 96
-WIRE 528 128 512 128
+WIRE 432 96 240 96
+WIRE 432 272 432 96
+WIRE 576 320 576 144
 WIRE 160 432 80 432
 WIRE 240 432 160 432
 WIRE 432 432 240 432
@@ -85,7 +85,7 @@ WIRE 480 896 480 880
 WIRE 848 928 848 912
 FLAG -448 176 0
 FLAG 240 176 0
-FLAG 576 144 0
+FLAG 576 320 0
 FLAG 864 160 0
 FLAG 848 -96 Vprotect
 FLAG 576 32 Vctl
@@ -115,11 +115,6 @@ WINDOW 123 0 0 Left 2
 WINDOW 39 0 0 Left 2
 SYMATTR Value EXP(0 202 5ms 10ms 0s 220ms)
 SYMATTR InstName V1
-SYMBOL zener 256 16 R180
-WINDOW 0 24 64 Left 2
-WINDOW 3 24 0 Left 2
-SYMATTR InstName D1
-SYMATTR Value DFLZ33
 SYMBOL res 224 0 R0
 SYMATTR InstName R1
 SYMATTR Value 2K
@@ -265,9 +260,11 @@ SYMATTR InstName C8
 SYMATTR Description Capacitor
 SYMATTR Type cap
 SYMATTR SpiceLine V=50 Irms=22m Rser=3.9 Lser=0 mfg="Nichicon" pn="UPL1HR47MAH" type="Al electrolytic"
-SYMBOL nmos 528 48 R0
-SYMATTR InstName M1
-TEXT -480 280 Left 2 !.tran 3s
+SYMBOL UserLib\\Z-Diodes\ from\ DiodesInc\\Xzener_DiodesInc 592 144 R180
+WINDOW 38 24 -21 Left 2
+SYMATTR InstName U2
+SYMATTR SpiceModel SMAZ27
+TEXT -480 280 Left 2 !.tran .6s
 TEXT -504 -152 Left 2 ;This simulates a Load Dump on a 24v System
 TEXT 544 -552 Left 2 ;Analog Input intrinsic diode and\nsmall R for current measurement
 TEXT 480 408 Bottom 2 ;LT3682 - 1A µPower Step-Down Switching Regulator\nInput:  6.9V - 36V(Transients to 60V)   Output: 5V @ 1A